Phase and magnitude detectors are common circuits used in communication systems. FM stereo decoders use the phase detector as a part of the phase-locked loop (PLL). The PLL is used to lock to the 19 kHz pilot signal added to the FM composite for synchronization of the transmitter and receiver. The magnitude detector is used to detect the presence of the pilot. The presence of a valid pilot impacts the audio processing of the signal and controls illumination of a stereo indicator light.
FIG. 1 shows a block diagram of a conventional PLL of an FM stereo decoder. The input composite is applied to a phase detector, which develops a DC error voltage proportional to the difference in phase between the pilot and the 19 kHz signal fed back to the detector. The output of the phase detector passes through a loop filter and is applied to a voltage controlled oscillator (VCO). The error voltage drives the output of the VCO to produce a 76 kHz signal in phase with the 19 kHz pilot. The output of the VCO is divided to provide an in-phase 38 kHz and both in-phase and quadrature 19 kHz signals. The 38 kHz signal is used to decode the input composite. The in-phase and quadrature 19 kHz provide the other inputs to phase and magnitude detectors. When the input pilot and VCO feedback are in phase, the DC output of the phase detector is zero.
The composite input is also fed to a magnitude detector the output of which is fed to a lowpass filter to generate a DC signal proportional to the amplitude of the 19 kHz pilot. This DC signal is compared with a reference voltage in a comparator to generate a digital output. If the magnitude detector output is greater than the reference, the comparator is high and a valid pilot is indicated. Otherwise, the comparator output is low, and a monophonic input signal is presumed. When the input pilot and VCO feedback are in phase, the DC output of the magnitude detector is maximum.
The magnitude and phase detectors discussed above may take the form of simple multipliers clocked by 50 percent duty cycle 19 kHz clock signals. The only difference between the two detectors is the fact that the clock signals for the magnitude detector are phase displaced by 90 degrees from the clock signals of the phase detector. These multipliers can be implemented in CMOS or bipolar technology and are well known to those skilled in the art.
If the input to the multiplier used for phase or magnitude detection is a sinewave as shown in FIG. 2A (19 kHz in the above example), multiplication by a squarewave of the same frequency will produce a DC voltage proportional to either the phase or magnitude of the sinewave. In a PLL, the output of the phase detector is forced to be zero through feedback. The squarewave shown in FIG. 2B, when multiplied with the sinewave of FIG. 2A, produces the waveform of FIG. 2C. The multiplication process can be thought of as reversing the polarity of the sinewave at a rate equal to the frequency of the squarewave. In this case, the input sinusoid is being multiplied by plus one or minus one to generate the output. If the phase relationship between the input and the clock are as displayed in FIGS. 2A and 2B, the low passed output will be zero volts as shown in FIG. 2D. The low passed output will move away from zero volts as the phase difference between the input and clock signal changes from zero degrees. The PLL acts as a low pass filter and only responds to the DC of the waveform in FIG. 2C.
The clock signal of the magnitude detector is shown in FIG. 2E and is shifted 90 degrees from the phase detector clock of FIG. 2B. When the incoming sinewave is multiplied by this squarewave, the resulting output will be a rectified version of the input as shown in FIG. 2F. This signal is low pass filtered to generate a DC voltage directly proportional to the magnitude of the incoming sinewave as shown in FIG. 2G.
The conventional multiplying detectors described with reference to FIG. 2 provide suitable responses for many applications. The main problem with this type of detector is that the circuit responds to all odd harmonics of the squarewave clocking signal. Referring to FIG. 3A the transient response of the squarewave clock signal of the magnitude detector is shown. As is well known the signal contains frequency components which are integer multiples of the fundamental (in this case 19 kHz). A single frequency component in the time domain is represented as an impulse in the frequency domain of amplitude proportional to the amplitude of the component (a sinewave would have one impulse at the fundamental frequency). A squarewave exhibits odd harmonics. Thus a 19 kHz squareware contains components at 19 kHz, 57 kHz, 95 kHz etc as shown in FIG. 3B. FIGS. 3C and 3D show the transient and frequency response of the squarewave clock signal of the phase detector. It differs from the magnitude detector frequency response due to the opposite sign of every other harmonic.
Information at 95 kHz and beyond is not important to the performance of a FM stereo decoder system because it is outside the bandwidth of interest; however, 57 kHz can be of significant importance. The addition of information beyond the FM composite bandwidth of 53 kHz is being considered in both Europe and the United States. For example, Advanced Road Information (ARI) and Radio Data System (RDS) contain pilot information at and about 57 kHz. Standard magnitude and phase detector circuits such as described above, using 50 percent duty cycle squarewave clock signals, are adversely affected by the ARI and RDS signals. The frequency response of these clock signals indicates this; however, a discussion of the time response will best illustrate the problems.
Referring to FIG. 4A, two in-phase input sinewaves, one at 19 kHz and one at 57 kHz are shown. FIG. 4B shows the 19 kHz phase detector squarewave which is the same as shown in FIG. 2B. FIGS. 4C and 4D show the transient and DC output of the phase detector, respectively, to a 57 kHz input. The output DC is still zero; however, the phase response is negative at 57 kHz and will reduce the gain of the 19 kHz phase detector. This is because the frequency response of the third harmonic is opposite in sign to the fundamental, as shown in FIG. 3D. The reduction in gain has a negative impact on the characteristics of the PLL. FIG. 4E shows the 19 kHz magnitude detector squarewave clock signal while FIGS. 4F AND 4G show the transient and DC output of the magnitude detector, respectively, to a 57 kHz input. The DC output is not zero, and will have an adverse effect in detecting the magnitude of the 19 kHz pilot.
Switched capacitor sinewave multipliers have been proposed for use in various applications. See for example, "Switched-Capacitor Stereo Decoders for T.V. and Radio Receivers", IEEE Transactions on Consumer Electronics, Vol. CE-31, No. 3, Aug. 1985 which proposes using a switched capacitor sinewave multiplier as a phase detector. The sinusoidal phase detector is used to avoid the information at 57 kHz. The sine wave, by definition, has no harmonic content and only the desired 19 kHz pilot will affect the circuit.
While the sinusoidal detectors will avoid the problems of odd harmonics adversely impacting the operation of the system, they require a complicated capacitor array as well as a complicated clocking scheme. The digital logic used to generate the clocks is reasonably small, but the capacitor arrays can become large and difficult to layout in the integrated circuit. Also, it would obviously be impossible to lock on to a 57 kHz pilot, with this phase detector, if that function was desired.